1. Field of the Invention
The present invention relates to semiconductor packages including dies of semiconductor chips that are flip-chip mounted on circuit boards, and to semiconductor package modules including the semiconductor packages and the circuit boards.
2. Description of the Related Art
At present, chip scale package (CSP) modules including dies of semiconductor chips and circuit boards on which the dies are flip-chip mounted have been in use in various fields.
As Japanese Unexamined Patent Application Publication No. 11-274374 describes, semiconductor package modules such as the CSP modules, include a die (wafer) having bonding pads arranged on a main surface thereof and a passivation layer arranged so as to expose the bonding pads therethrough. Furthermore, a protective film made of, for example, polyimide is provided on the surface of the passivation layer. In addition, an under-bump metal (UBM) is provided on each bonding pad so as to connect the bonding pads arranged adjacent to the die rather than to the passivation layer and the protective film to an external circuit board, and solder bumps are provided on the surfaces of the UBMs.
FIG. 7A is a cross-sectional view illustrating the structure of a known semiconductor package 10K used for the semiconductor package module 1K, and FIG. 7B is a cross-sectional view illustrating the structure of a known semiconductor package module 1K. In FIGS. 7A and 7B, lands and solder bumps used for mounting the semiconductor package module 1K to an external circuit board are not illustrated.
As shown in FIG. 7A, the known semiconductor package 10K includes a semiconductor IC die 11, and bonding pads 12 are two-dimensionally arranged on a mounting surface 11F of the die 11. A passivation layer 13 is provided on the mounting surface 11F of the die 11 such that a central area of each bonding pad 12 is open. Furthermore, a protective film 14 is provided so as to cover the passivation layer 13 such that the central area of each bonding pad 12 is exposed therethrough.
A UBM 15K is provided on the surface of each bonding pad 12 so as to be exposed over the surface of the protective film 14 adjacent to the outside.
Presently, all of the UBMs 15K usually have the same diameter. That is, the diameter φc of the UBM 15KC at the center of the die 11 and the diameter φe of the UBM 15KE at an end of the die 11 are the same. Herein, the diameter of the UBMs refers to that of the UBMs 15K when viewed in a direction perpendicular to the mounting surface 11F of the die 11. More specifically, it refers to the diameter of portions enclosed by the protective film 14 connected to the bonding pads 12.
In addition, solder bumps 16 are provided on the surfaces of the UBMs 15K having the same shape as described above.
The semiconductor package 10K is flip-chip mounted on a circuit board 20. That is, the semiconductor package 10K is arranged such that the mounting surface 11F thereof faces the circuit board 20 and such that the solder bumps 16 face corresponding mounting lands 21 of the circuit board 20. Subsequently, a reflow process, for example, is performed so that the UBMs 15K of the semiconductor package 10K and the mounting lands 21 of the circuit board 20 are electrically connected by the solder bumps 16.
In the above-described known structure, the positional relationship between the bonding pads 12 (UBMs 15K) of the semiconductor package 10K and the mounting lands 21 of the circuit board 20 may change due to differences in the thermal expansion coefficient between the circuit board 20 and the die 11, and the solder bumps 16 may rupture due to the stress caused by the change in the positional relationship.
Moreover, when stress, such as bending stress, is applied from the outside to the CSP module 1K, the positional relationship between the bonding pads 12 (UBMs 15K) of the semiconductor package 10K and the mounting lands 21 of the circuit board 20 may change due to differences in the degree of bending between the circuit board 20 and the die 11, and the solder bumps 16 may rupture due to the stress caused by the change in the positional relationship.
In the known structure, a resin seal 30 that reduces stress occurring in the connecting structure between the semiconductor package 10K and the circuit board 20 is arranged so as to cover the connecting portions using the solder bumps 16, and prevents the rupture of the solder bumps 16.
However, in the above-described known structure, resin sealing, which is not directly related to functional connection (mounting), is required after the functional connection, and causes an increase in workload accordingly. It also requires resin which is an additional constituent material. Therefore, the semiconductor package module becomes expensive due to components that are not directly required for functional needs.